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Text File  |  2000-02-28  |  10KB  |  230 lines
  1. #ifndef WARPUP_MACROS_H
  2. #define WARPUP_MACROS_H
  3.  
  4. #define PPCLIBCALLASM    "\n\
  5.     stwu    1,-32(1)\n\
  6.     mtlr    0\n\
  7.     blrl\n\
  8.     la    1,32(1)\n\
  9.     "
  10.  
  11. #define PPCLP0(base,offs,rt)                    \
  12. ({                                \
  13.     register rt returnreg __asm("3");            \
  14.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  15.     __asm volatile(PPCLIBCALLASM                \
  16.     :"=r" (returnreg)                    \
  17.     :"r" (dummy)                        \
  18.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  19.     returnreg;\
  20. })
  21.  
  22. #define PPCLP0NR(base,offs)                    \
  23. ({                                \
  24.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  25.     __asm volatile(PPCLIBCALLASM                \
  26.     :                            \
  27.     :"r" (dummy)                        \
  28.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  29. })
  30.  
  31. #define PPCLP1(base,offs,rt,t1,r1,v1)                \
  32. ({                                \
  33.     register rt returnreg __asm("3");            \
  34.     register t1 param1 __asm(#r1)=(v1);            \
  35.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  36.     __asm volatile(PPCLIBCALLASM                \
  37.     :"=r" (returnreg)                    \
  38.     :"r" (dummy),"r" (param1)                \
  39.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  40.     returnreg;\
  41. })
  42.  
  43. #define PPCLP1NR(base,offs,t1,r1,v1)                \
  44. ({                                \
  45.     register t1 param1 __asm(#r1)=(v1);            \
  46.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  47.     __asm volatile(PPCLIBCALLASM                \
  48.     :                            \
  49.     :"r" (dummy),"r" (param1)                \
  50.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  51. })
  52.  
  53. #define PPCLP2(base,offs,rt,t1,r1,v1,t2,r2,v2)            \
  54. ({                                \
  55.     register rt returnreg __asm("3");            \
  56.     register t1 param1 __asm(#r1)=(v1);            \
  57.     register t2 param2 __asm(#r2)=(v2);            \
  58.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  59.     __asm volatile(PPCLIBCALLASM                \
  60.     :"=r" (returnreg)                    \
  61.     :"r" (dummy),"r" (param1),"r" (param2)            \
  62.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  63.     returnreg;\
  64. })
  65.  
  66. #define PPCLP2NR(base,offs,t1,r1,v1,t2,r2,v2)            \
  67. ({                                \
  68.     register t1 param1 __asm(#r1)=(v1);            \
  69.     register t2 param2 __asm(#r2)=(v2);            \
  70.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  71.     __asm volatile(PPCLIBCALLASM                \
  72.     :                            \
  73.     :"r" (dummy),"r" (param1),"r" (param2)            \
  74.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  75. })
  76.  
  77. #define PPCLP3(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3)        \
  78. ({                                \
  79.     register rt returnreg __asm("3");            \
  80.     register t1 param1 __asm(#r1)=(v1);            \
  81.     register t2 param2 __asm(#r2)=(v2);            \
  82.     register t3 param3 __asm(#r3)=(v3);            \
  83.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  84.     __asm volatile(PPCLIBCALLASM                \
  85.     :"=r" (returnreg)                    \
  86.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3)    \
  87.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  88.     returnreg;\
  89. })
  90.  
  91. #define PPCLP3NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3)        \
  92. ({                                \
  93.     register t1 param1 __asm(#r1)=(v1);            \
  94.     register t2 param2 __asm(#r2)=(v2);            \
  95.     register t3 param3 __asm(#r3)=(v3);            \
  96.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  97.     __asm volatile(PPCLIBCALLASM                \
  98.     :                            \
  99.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3)    \
  100.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  101. })
  102.  
  103. #define PPCLP4(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4)\
  104. ({                                \
  105.     register rt returnreg __asm("3");            \
  106.     register t1 param1 __asm(#r1)=(v1);            \
  107.     register t2 param2 __asm(#r2)=(v2);            \
  108.     register t3 param3 __asm(#r3)=(v3);            \
  109.     register t4 param4 __asm(#r4)=(v4);            \
  110.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  111.     __asm volatile(PPCLIBCALLASM                \
  112.     :"=r" (returnreg)                    \
  113.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4)    \
  114.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  115.     returnreg;\
  116. })
  117.  
  118. #define PPCLP4NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4)        \
  119. ({                                \
  120.     register t1 param1 __asm(#r1)=(v1);            \
  121.     register t2 param2 __asm(#r2)=(v2);            \
  122.     register t3 param3 __asm(#r3)=(v3);            \
  123.     register t4 param4 __asm(#r4)=(v4);            \
  124.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  125.     __asm volatile(PPCLIBCALLASM                \
  126.     :                            \
  127.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4)    \
  128.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  129. })
  130.  
  131. #define PPCLP5(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5)\
  132. ({                                \
  133.     register rt returnreg __asm("3");            \
  134.     register t1 param1 __asm(#r1)=(v1);            \
  135.     register t2 param2 __asm(#r2)=(v2);            \
  136.     register t3 param3 __asm(#r3)=(v3);            \
  137.     register t4 param4 __asm(#r4)=(v4);            \
  138.     register t5 param5 __asm(#r5)=(v5);            \
  139.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  140.     __asm volatile(PPCLIBCALLASM                \
  141.     :"=r" (returnreg)                    \
  142.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5)    \
  143.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  144.     returnreg;\
  145. })
  146.  
  147. #define PPCLP5NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5)        \
  148. ({                                \
  149.     register t1 param1 __asm(#r1)=(v1);            \
  150.     register t2 param2 __asm(#r2)=(v2);            \
  151.     register t3 param3 __asm(#r3)=(v3);            \
  152.     register t4 param4 __asm(#r4)=(v4);            \
  153.     register t5 param5 __asm(#r5)=(v5);            \
  154.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  155.     __asm volatile(PPCLIBCALLASM                \
  156.     :                            \
  157.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5)    \
  158.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  159. })
  160.  
  161. #define PPCLP6(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5,t6,r6,v6)\
  162. ({                                \
  163.     register rt returnreg __asm("3");            \
  164.     register t1 param1 __asm(#r1)=(v1);            \
  165.     register t2 param2 __asm(#r2)=(v2);            \
  166.     register t3 param3 __asm(#r3)=(v3);            \
  167.     register t4 param4 __asm(#r4)=(v4);            \
  168.     register t5 param5 __asm(#r5)=(v5);            \
  169.     register t6 param6 __asm(#r6)=(v6);            \
  170.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  171.     __asm volatile(PPCLIBCALLASM                \
  172.     :"=r" (returnreg)                    \
  173.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5),"r" (param6)    \
  174.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  175.     returnreg;\
  176. })
  177.  
  178. #define PPCLP6NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5,t6,r6,v6)        \
  179. ({                                \
  180.     register t1 param1 __asm(#r1)=(v1);            \
  181.     register t2 param2 __asm(#r2)=(v2);            \
  182.     register t3 param3 __asm(#r3)=(v3);            \
  183.     register t4 param4 __asm(#r4)=(v4);            \
  184.     register t5 param5 __asm(#r5)=(v5);            \
  185.     register t6 param6 __asm(#r6)=(v6);            \
  186.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  187.     __asm volatile(PPCLIBCALLASM                \
  188.     :                            \
  189.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5),"r" (param6)    \
  190.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  191. })
  192.  
  193.  
  194. #define PPCLP7(base,offs,rt,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5,t6,r6,v6,t7,r7,v7)\
  195. ({                                \
  196.     register rt returnreg __asm("3");            \
  197.     register t1 param1 __asm(#r1)=(v1);            \
  198.     register t2 param2 __asm(#r2)=(v2);            \
  199.     register t3 param3 __asm(#r3)=(v3);            \
  200.     register t4 param4 __asm(#r4)=(v4);            \
  201.     register t5 param5 __asm(#r5)=(v5);            \
  202.     register t6 param6 __asm(#r6)=(v6);            \
  203.     register t7 param7 __asm(#r7)=(v7);            \
  204.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  205.     __asm volatile(PPCLIBCALLASM                \
  206.     :"=r" (returnreg)                    \
  207.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5),"r" (param6),"r" (param7)    \
  208.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  209.     returnreg;\
  210. })
  211.  
  212. #define PPCLP8NR(base,offs,t1,r1,v1,t2,r2,v2,t3,r3,v3,t4,r4,v4,t5,r5,v5,t6,r6,v6,t7,r7,v7,t8,r8,v8)        \
  213. ({                                \
  214.     register t1 param1 __asm(#r1)=(v1);            \
  215.     register t2 param2 __asm(#r2)=(v2);            \
  216.     register t3 param3 __asm(#r3)=(v3);            \
  217.     register t4 param4 __asm(#r4)=(v4);            \
  218.     register t5 param5 __asm(#r5)=(v5);            \
  219.     register t6 param6 __asm(#r6)=(v6);            \
  220.     register t7 param7 __asm(#r7)=(v7);            \
  221.     register t8 param8 __asm(#r8)=(v8);
  222.     register unsigned long dummy __asm("0") = *(unsigned long *)((char *)base+2+offs); \
  223.     __asm volatile(PPCLIBCALLASM                \
  224.     :                            \
  225.     :"r" (dummy),"r" (param1),"r" (param2),"r" (param3),"r" (param4),"r" (param5),"r" (param6),"r" (param7),"r" (param8)    \
  226.     :"0","3","4","5","6","7","8","9","10","11","12","32","33","34","35","36","37","38","39","40","41","42","43","44","45","ctr","lr","cc","memory");\
  227. })
  228.  
  229. #endif
  230.